| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV][GlobalISel] Select and expand global addresses | Richard-Qin-X | 2026-08-19 | 1 | -0/+1 |
| * | [CodeGen] Match LLVM Legalizer ownership | Richard-Qin-X | 2026-08-14 | 1 | -0/+4 |
| * | [CodeGen] Unify scalar low-level types | Richard-Qin-X | 2026-08-13 | 1 | -8/+10 |
| * | [CodeGen] Match LLVM branch relaxation semantics | Richard-Qin-X | 2026-08-13 | 1 | -0/+1 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -0/+1 |
| * | [CodeGen] Implement machine SSA exit | Richard-Qin-X | 2026-08-08 | 1 | -0/+1 |
| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 1 | -0/+49 |
| * | [MIR] Complete document parsing and printing | Richard-Qin-X | 2026-08-07 | 1 | -0/+1 |
| * | [CodeGen] Add transactional MachineIR builder | Richard-Qin-X | 2026-08-01 | 1 | -0/+26 |
| * | [CodeGen] Add machine instruction descriptors | Richard-Qin-X | 2026-08-01 | 1 | -0/+264 |
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