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path: root/backend/include/rcc/CodeGen/MachineOperand.h
Commit message (Expand)AuthorAgeFilesLines
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-221-3/+4
* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-191-1/+4
* [GlobalISel] Legalize G_ABSRichard-Qin-X2026-08-141-0/+1
* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-131-0/+2
* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-131-72/+6
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-111-0/+1
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-091-0/+1
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-081-0/+1
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-071-0/+3
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-031-4/+174
* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-021-2/+3
* [CodeGen] Add machine instruction descriptorsRichard-Qin-X2026-08-011-0/+1
* [CodeGen] Build the core MachineIR object modelRichard-Qin-X2026-08-011-0/+344
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 11:26:19 +0000