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* [GlobalISel] Legalize G_ABSRichard-Qin-X2026-08-145-21/+32
* [RISCV] Legalize va_copy intrinsicsRichard-Qin-X2026-08-141-43/+36
* [MIR] Normalize explicit successor probabilitiesRichard-Qin-X2026-08-141-0/+3
* [GlobalISel] Match LLVM legalization value trackingRichard-Qin-X2026-08-147-426/+525
* [CodeGen] Match LLVM Legalizer ownershipRichard-Qin-X2026-08-1412-8/+2328
* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-135-77/+55
* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-134-11/+28
* [CodeGen] Match LLVM branch relaxation semanticsRichard-Qin-X2026-08-131-0/+1
* [RISCV] Match LLVM register bank mappingsRichard-Qin-X2026-08-132-5/+18
* [MIR] Omit predictable successors in simplified outputRichard-Qin-X2026-08-131-0/+7
* [CodeGen] Remove duplicate analysis declarationsRichard-Qin-X2026-08-132-5/+0
* [CodeGen] Remove the unused property queryRichard-Qin-X2026-08-131-1/+0
* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-135-181/+5
* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-135-118/+23
* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-134-0/+426
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-1337-822/+380
* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-139-416/+542
* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-133-49/+62
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-121-8/+4
* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-128-163/+222
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-125-51/+31
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-129-28/+28
* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-121-0/+72
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-121-0/+1
* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-121-1/+0
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-0/+9
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-6/+0
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-111-1/+6
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-116-3/+330
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1010-25/+136
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-095-0/+403
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0936-0/+1501
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-096-0/+174
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0917-16/+1154
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-093-0/+414
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-086-4/+94
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-082-0/+157
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-077-0/+1720
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-0/+49
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-071-0/+7
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-079-22/+351
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-042-0/+82
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-036-20/+272
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-035-4/+475
* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-027-3/+194
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-022-0/+141
* [CodeGen] Track debug instruction identitiesRichard-Qin-X2026-08-013-0/+45
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-012-0/+124
* [CodeGen] Add MIR function and block attributesRichard-Qin-X2026-08-016-18/+353
* [MIR] Add compilation unit reference contextRichard-Qin-X2026-08-011-0/+61
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 14:27:19 +0000