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* [Support] Centralize error context handlingRichard-Qin-X2026-08-131-0/+2
* [CodeGen] Remove the unused property queryRichard-Qin-X2026-08-131-1/+0
* [TableGen] Split the target description generatorRichard-Qin-X2026-08-132-0/+255
* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-138-61/+128
* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-138-118/+176
* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-138-231/+167
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-1342-826/+1142
* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-139-416/+542
* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-133-49/+62
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-126-104/+50
* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-129-169/+229
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-126-54/+31
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-1210-30/+30
* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-121-5/+0
* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-124-30/+78
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-122-0/+2
* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-124-5/+0
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-0/+9
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-121-0/+2
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-111-1/+2
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-6/+0
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-114-1/+64
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-111-0/+63
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-119-3/+349
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1020-25/+754
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-0917-0/+722
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-0917-0/+1205
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0938-0/+1518
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-098-0/+177
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0920-19/+1160
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-093-0/+414
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-087-4/+95
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-083-0/+173
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-078-0/+1763
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-072-2/+102
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-072-0/+30
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-0714-25/+611
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-044-0/+212
* [MIR] Add machine instruction lexerRichard-Qin-X2026-08-031-0/+181
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-036-20/+272
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-035-4/+475
* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-027-3/+194
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-022-0/+141
* [CodeGen] Track debug instruction identitiesRichard-Qin-X2026-08-013-0/+45
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-012-0/+124
* [CodeGen] Add MIR function and block attributesRichard-Qin-X2026-08-016-18/+353
* [MIR] Add compilation unit reference contextRichard-Qin-X2026-08-012-0/+236
* [Support] Add MIR YAML parsing infrastructureRichard-Qin-X2026-08-012-0/+280
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-016-11/+303
* [CodeGen] Add target state and compilation statusRichard-Qin-X2026-08-014-0/+389
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 12:02:43 +0000