| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [CodeGen] Match LLVM Legalizer ownership | Richard-Qin-X | 2026-08-14 | 1 | -0/+13 |
| * | [CodeGen] Unify scalar low-level types | Richard-Qin-X | 2026-08-13 | 1 | -11/+13 |
| * | [RISCV] Split the GlobalISel target components | Richard-Qin-X | 2026-08-12 | 1 | -4/+3 |
| * | [MIR] Accept fixed-baseline LLVM syntax | Richard-Qin-X | 2026-08-11 | 1 | -2/+6 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -1/+1 |
| * | [CodeGen] Implement machine SSA exit | Richard-Qin-X | 2026-08-08 | 1 | -3/+5 |
| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 1 | -40/+175 |
| * | [CodeGen] Add target register descriptions | Richard-Qin-X | 2026-08-01 | 1 | -8/+0 |
| * | [CodeGen] Add transactional MachineIR builder | Richard-Qin-X | 2026-08-01 | 1 | -66/+157 |
| * | [CodeGen] Add machine instruction descriptors | Richard-Qin-X | 2026-08-01 | 1 | -0/+531 |
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