| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [CodeGen] Implement machine SSA exit | Richard-Qin-X | 2026-08-08 | 1 | -3/+5 |
| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 1 | -40/+175 |
| * | [CodeGen] Add target register descriptions | Richard-Qin-X | 2026-08-01 | 1 | -8/+0 |
| * | [CodeGen] Add transactional MachineIR builder | Richard-Qin-X | 2026-08-01 | 1 | -66/+157 |
| * | [CodeGen] Add machine instruction descriptors | Richard-Qin-X | 2026-08-01 | 1 | -0/+531 |
