rcc-project - A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[CodeGen] Bind virtual register types once	Richard-Qin-X	2026-08-29	1	-2/+3
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*	[GlobalISel] Match LLVM legalization value tracking	Richard-Qin-X	2026-08-14	1	-4/+16
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*	[CodeGen] Match LLVM Legalizer ownership	Richard-Qin-X	2026-08-14	1	-0/+21
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*	[CodeGen] Unify scalar low-level types	Richard-Qin-X	2026-08-13	1	-4/+6
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*	[RISCV] Match LLVM register bank mappings	Richard-Qin-X	2026-08-13	1	-0/+4
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*	[MIR] Accept fixed-baseline LLVM syntax	Richard-Qin-X	2026-08-11	1	-0/+1
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*	[CodeGen] Complete register allocation infrastructure	Richard-Qin-X	2026-08-09	1	-0/+5
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*	[CodeGen] Add target MIR text schema	Richard-Qin-X	2026-08-03	1	-0/+13
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*	[CodeGen] Add strict MachineIR verification	Richard-Qin-X	2026-08-01	1	-0/+22
\| \| \| \|	Verify arena catalogs, intrusive layouts, reciprocal CFG edges, operand ownership, exact def-use coverage, instruction descriptors, pseudo deadlines, and MachineFunctionProperties. Preserve monotonic-arena history while rejecting detached objects that retain live state.
*	[CodeGen] Build the core MachineIR object model	Richard-Qin-X	2026-08-01	1	-0/+362
	Add arena-owned, address-stable MachineFunction, MachineBasicBlock, and MachineInstr nodes with intrusive layout and instruction lists. Model every required MachineOperand category, reciprocal ties, source state, and immutable per-instruction memory references. Implement physical and virtual register def-use chains whose back-links survive operand vector moves, plus vreg properties, tombstones, live-ins, reserved registers, and atomic CFG updates. Exercise ownership, reallocation, unlink/relink, cross-function rejection, and sanitizer paths.