| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV][GlobalISel] Generate integer comparisons | Richard-Qin-X | 2026-08-16 | 1 | -3/+10 |
| * | [GlobalISel] Lower stack operations | Richard-Qin-X | 2026-08-15 | 1 | -2/+9 |
| * | [GlobalISel] Match LLVM legalization value tracking | Richard-Qin-X | 2026-08-14 | 1 | -2/+4 |
| * | [CodeGen] Unify scalar low-level types | Richard-Qin-X | 2026-08-13 | 1 | -1/+1 |
| * | [CodeGen] Implement machine SSA exit | Richard-Qin-X | 2026-08-08 | 1 | -1/+7 |
| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 1 | -5/+12 |
| * | [CodeGen] Add target MIR text schema | Richard-Qin-X | 2026-08-03 | 1 | -2/+132 |
| * | [CodeGen] Model complete MIR operands | Richard-Qin-X | 2026-08-03 | 1 | -0/+7 |
| * | [CodeGen] Add target register descriptions | Richard-Qin-X | 2026-08-01 | 1 | -0/+610 |
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