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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-123-7/+5
* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-126-747/+948
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-127-29/+26
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-129-21/+33
* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-126-5/+242
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-122-11/+25
* [CodeGen] Verify local physical live-insRichard-Qin-X2026-08-121-3/+73
* [CodeGen] Allow dynamic implicit operands on copiesRichard-Qin-X2026-08-121-1/+1
* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-121-1/+0
* [CodeGen] Allow narrow atomic RMW memory typesRichard-Qin-X2026-08-121-1/+1
* [CodeGen] Preserve variable-sized stack object offsetsRichard-Qin-X2026-08-121-6/+2
* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-121-22/+4
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-0/+1
* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-122-9/+8
* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-121-1/+10
* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-121-4/+12
* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-111-0/+11
* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-111-2/+2
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-10/+9
* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-12/+11
* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-111-2/+2
* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-111-3/+4
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-112-26/+76
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-1110-73/+165
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1022-124/+573
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-093-4/+14
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-094-0/+371
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0932-1/+8164
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-0912-7/+551
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0922-78/+2575
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-096-32/+1931
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-088-49/+1597
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-082-0/+619
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-076-0/+4100
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-40/+175
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-072-7/+40
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-0711-24/+1449
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-044-1/+200
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-038-21/+643
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-038-1/+600
* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-0210-11/+285
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-024-0/+125
* [CodeGen] Track debug instruction identitiesRichard-Qin-X2026-08-015-0/+143
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-014-0/+263
* [CodeGen] Add MIR function and block attributesRichard-Qin-X2026-08-017-8/+171
* [MIR] Add compilation unit reference contextRichard-Qin-X2026-08-012-0/+123
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-017-36/+1259
* [CodeGen] Add target state and compilation statusRichard-Qin-X2026-08-016-0/+415
* [CodeGen] Add constant and jump table stateRichard-Qin-X2026-08-018-16/+798
* [CodeGen] Add MachineFrameInfoRichard-Qin-X2026-08-015-5/+385
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 12:00:55 +0000