aboutsummaryrefslogtreecommitdiff
path: root/backend/lib/CodeGen
Commit message (Expand)AuthorAgeFilesLines
* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-264-41/+367
* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-2512-40/+425
* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-253-0/+9
* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-253-3/+621
* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-242-0/+432
* [RISCV] Match LLVM large call frame loweringRichard-Qin-X2026-08-242-9/+13
* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-244-11/+8
* [CodeGen] Match LLVM machine combiner semanticsRichard-Qin-X2026-08-243-240/+146
* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-244-51/+3
* [CodeGen] Implement RISC-V peephole branch optimizationRichard-Qin-X2026-08-243-1/+104
* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-224-1/+54
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-228-38/+347
* [CodeGen] Match LLVM final verifier contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Match LLVM finalization contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Match LLVM late pseudo contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Remove RCC fallthrough normalizationRichard-Qin-X2026-08-193-169/+0
* [CodeGen] Match LLVM block placement contractRichard-Qin-X2026-08-191-6/+2
* [CodeGen] Unify LLVM branch folding pipelineRichard-Qin-X2026-08-194-424/+304
* [CodeGen] Match LLVM tail duplication contractRichard-Qin-X2026-08-191-9/+1
* [CodeGen] Match LLVM post-machine scheduler contractRichard-Qin-X2026-08-191-7/+1
* [CodeGen] Match LLVM post-RA pseudo expansion contractRichard-Qin-X2026-08-191-7/+1
* [CodeGen] Remove non-LLVM machine DCE placementsRichard-Qin-X2026-08-191-6/+0
* [CodeGen] Remove unsupported post-frame combinerRichard-Qin-X2026-08-192-22/+0
* [CodeGen] Remove unsupported pre-PEI pseudo expansionRichard-Qin-X2026-08-192-39/+2
* [CodeGen] Match LLVM shrink wrapping contractRichard-Qin-X2026-08-191-7/+1
* [CodeGen] Match LLVM post-RA sink contractRichard-Qin-X2026-08-191-3/+1
* [CodeGen] Match LLVM post-RA LICM contractRichard-Qin-X2026-08-191-3/+1
* [CodeGen] Match LLVM post-RA combiner contractRichard-Qin-X2026-08-191-1/+1
* [CodeGen] Match LLVM stack slot coloring contractRichard-Qin-X2026-08-191-6/+1
* [CodeGen] Match LLVM PBQP allocator input contractRichard-Qin-X2026-08-191-4/+2
* [CodeGen] Match LLVM machine scheduler contractRichard-Qin-X2026-08-191-6/+1
* [CodeGen] Match LLVM machine sink input contractRichard-Qin-X2026-08-191-2/+2
* [CodeGen] Match LLVM prologepilog input contractRichard-Qin-X2026-08-191-2/+1
* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-193-3/+329
* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-194-5/+50
* [RISCV][GlobalISel] Generate integer load selectionRichard-Qin-X2026-08-191-0/+28
* [RISCV][GlobalISel] Match floating comparisonsRichard-Qin-X2026-08-192-10/+50
* [RISCV][GlobalISel] Generate conditional branch selectionRichard-Qin-X2026-08-171-5/+27
* [RISCV][GlobalISel] Constrain core copies during selectionRichard-Qin-X2026-08-171-10/+14
* [GlobalISel] Remove redundant virtual copies after selectionRichard-Qin-X2026-08-171-2/+42
* [RISCV][GlobalISel] Generate integer extension selectionsRichard-Qin-X2026-08-171-33/+74
* [RISCV][GlobalISel] Generate shift selectionsRichard-Qin-X2026-08-162-46/+374
* [RISCV][GlobalISel] Generate integer comparisonsRichard-Qin-X2026-08-163-132/+570
* [RISCV][GlobalISel] Select comparisons against zeroRichard-Qin-X2026-08-161-18/+274
* tablegen: Generate GlobalISel match tablesRichard-Qin-X2026-08-162-0/+255
* [GlobalISel] Propagate no-fp-except flagsRichard-Qin-X2026-08-161-0/+37
* [GlobalISel] Delete dead instructions before selectionRichard-Qin-X2026-08-161-11/+1
* [RISCV][GlobalISel] Select constant operands as immediatesRichard-Qin-X2026-08-162-7/+24
* [GlobalISel] Clear virtual register types after selectionRichard-Qin-X2026-08-152-2/+6
* [GlobalISel] Preserve MIR live-ins during selectionRichard-Qin-X2026-08-151-20/+0
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 09:41:27 +0000