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CMakeLists.txt
Commit message (
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Author
Age
Files
Lines
*
[CMake] Remove unused clang-tidy file registration
Richard-Qin-X
2026-08-28
1
-31
/
+2
|
*
[RISCV] Generate complete Zcmp instruction definitions
Richard-Qin-X
2026-08-28
1
-0
/
+1
|
*
[CodeGen] Add target machine registry
Richard-Qin-X
2026-08-28
1
-0
/
+3
|
*
[CodeGen] Separate assembly emission ownership
Richard-Qin-X
2026-08-28
1
-0
/
+6
|
*
[RISCV] Separate calling convention assignment
Richard-Qin-X
2026-08-28
1
-0
/
+4
|
*
[RISCV] Generate atomic RMW selection
Richard-Qin-X
2026-08-27
1
-0
/
+1
|
*
[RISCV] Implement push-pop optimization
Richard-Qin-X
2026-08-26
1
-0
/
+3
|
*
[CodeGen] Implement RISC-V finalize-isel
Richard-Qin-X
2026-08-26
1
-0
/
+3
|
*
[RISCV] Optimize W instructions
Richard-Qin-X
2026-08-26
1
-0
/
+1
|
*
[RISCV] Implement make-compressible pass
Richard-Qin-X
2026-08-25
1
-0
/
+3
|
*
[CodeGen] Implement RISC-V machine outlining
Richard-Qin-X
2026-08-25
1
-0
/
+1
|
*
[RISCV] Implement base offset merging
Richard-Qin-X
2026-08-25
1
-0
/
+2
|
*
[RISCV] Implement Zcmp move merging
Richard-Qin-X
2026-08-25
1
-0
/
+2
|
*
[RISCV] Generate MC pseudo lowering
Richard-Qin-X
2026-08-22
1
-0
/
+10
|
*
[CodeGen] Generate RISC-V macro fusion rules
Richard-Qin-X
2026-08-22
1
-0
/
+10
|
*
[GlobalISel] Generate prelegalizer combiner rules
Richard-Qin-X
2026-08-19
1
-0
/
+13
|
*
[RISCV][GlobalISel] Generate frame index selection
Richard-Qin-X
2026-08-19
1
-0
/
+1
|
*
[RISCV][GlobalISel] Generate conditional branch selection
Richard-Qin-X
2026-08-17
1
-0
/
+1
|
*
[RISCV][GlobalISel] Generate shift selections
Richard-Qin-X
2026-08-16
1
-0
/
+1
|
*
[RISCV][GlobalISel] Generate floating-point selections
Richard-Qin-X
2026-08-16
1
-1
/
+2
|
*
tablegen: Generate GlobalISel match tables
Richard-Qin-X
2026-08-16
1
-3
/
+31
|
*
[TableGen] Split the target description generator
Richard-Qin-X
2026-08-13
1
-2
/
+2
|
*
[RISCV] Split the GlobalISel target components
Richard-Qin-X
2026-08-12
1
-8
/
+16
|
*
[RISCV] Consolidate instruction behavior in RISCVInstrInfo
Richard-Qin-X
2026-08-12
1
-4
/
+7
|
*
[RISCV] Honor invocation subtarget features
Richard-Qin-X
2026-08-11
1
-0
/
+4
|
*
[RISCV] Legalize fixed-baseline RV64 MachineIR
Richard-Qin-X
2026-08-11
1
-0
/
+8
|
*
[Tooling] Complete backend tooling and validation
Richard-Qin-X
2026-08-10
1
-0
/
+4
|
*
[MC] Implement RV64GC object emission
Richard-Qin-X
2026-08-09
1
-0
/
+18
|
*
[MC] Implement RV64GC assembly emission
Richard-Qin-X
2026-08-09
1
-1
/
+19
|
*
[CodeGen] Implement machine optimization and scheduling
Richard-Qin-X
2026-08-09
1
-0
/
+18
|
*
[CodeGen] Implement RV64GC frame lowering
Richard-Qin-X
2026-08-09
1
-0
/
+3
|
*
[CodeGen] Complete register allocation infrastructure
Richard-Qin-X
2026-08-09
1
-0
/
+3
|
*
[CodeGen] Implement RV64GC legalization and instruction selection
Richard-Qin-X
2026-08-08
1
-0
/
+4
|
*
[CodeGen] Complete machine pass and ABI lowering infrastructure
Richard-Qin-X
2026-08-07
1
-0
/
+4
|
*
[RISCV] Complete RV64GC instruction description
Richard-Qin-X
2026-08-07
1
-8
/
+26
|
*
[RISCV] Add generated RV64GC register description
Richard-Qin-X
2026-08-07
1
-0
/
+79
Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
