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path: root/backend/lib/Target/RISCV/RISCV.rccdesc
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* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-121-15/+15
* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-121-1/+1
* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-121-0/+50
* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-121-0/+39
* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-0/+15
* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-0/+163
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-121-3/+5
* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-111-43/+75
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-111-0/+19
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-4/+0
* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-111-0/+4
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-111-3/+24
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-091-0/+195
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-091-2/+55
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-091-11/+11
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-071-1/+2978
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-071-0/+220
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 13:31:28 +0000