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path: root/backend/lib/Target/RISCV/RISCVPipeline.cpp
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* [CodeGen] Add target machine registryRichard-Qin-X2026-08-281-6/+7
* [RISCV] Separate calling convention assignmentRichard-Qin-X2026-08-281-0/+1
* [RISCV] Implement push-pop optimizationRichard-Qin-X2026-08-261-2/+4
* [CodeGen] Implement RISC-V finalize-iselRichard-Qin-X2026-08-261-1/+10
* [RISCV] Optimize W instructionsRichard-Qin-X2026-08-261-0/+6
* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-251-1/+9
* [RISCV] Implement make-compressible passRichard-Qin-X2026-08-251-0/+6
* [RISCV] Implement base offset mergingRichard-Qin-X2026-08-251-0/+3
* [RISCV] Implement Zcmp move mergingRichard-Qin-X2026-08-251-0/+5
* [CodeGen] Implement CFI instruction insertionRichard-Qin-X2026-08-241-1/+5
* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-241-5/+12
* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-241-1/+3
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-221-10/+17
* [GlobalISel] Generate prelegalizer combiner rulesRichard-Qin-X2026-08-191-5/+5
* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-191-1/+5
* [RISCV][GlobalISel] Legalize floating-point remainderRichard-Qin-X2026-08-151-2/+2
* [GlobalISel] Lower integer operations to libcallsRichard-Qin-X2026-08-151-2/+9
* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-151-4/+5
* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-131-6/+14
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-131-10/+12
* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-131-3/+4
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-121-23/+17
* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-121-7/+9
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-121-4/+5
* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-121-14/+0
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-121-2/+11
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-111-6/+18
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-101-0/+162
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 16:25:59 +0000