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* [GlobalISel] Legalize RISC-V jump tablesRichard-Qin-X2026-08-152-0/+206
* [GlobalISel] Legalize multiply with overflowRichard-Qin-X2026-08-151-0/+7
* [RISCV][GlobalISel] Legalize floating-point classesRichard-Qin-X2026-08-151-1/+67
* [RISCV][GlobalISel] Legalize floating-point remainderRichard-Qin-X2026-08-153-17/+46
* [RISCV][GlobalISel] Widen integer-to-floating conversions to XLENRichard-Qin-X2026-08-151-0/+11
* [RISCV][GlobalISel] Legalize floating-point to integer conversionsRichard-Qin-X2026-08-152-38/+57
* [GlobalISel] Lower floating-point conversion libcallsRichard-Qin-X2026-08-152-54/+91
* [GlobalISel] Lower stack operationsRichard-Qin-X2026-08-151-1/+8
* [RISCV][GlobalISel] Preserve Zbb sign extensionsRichard-Qin-X2026-08-152-1/+6
* [RISCV][GlobalISel] Legalize scalar bit count operationsRichard-Qin-X2026-08-151-12/+49
* [GlobalISel] Lower byte-swap operationsRichard-Qin-X2026-08-151-1/+5
* [GlobalISel] Use generic compare-exchange legalizationRichard-Qin-X2026-08-151-295/+5
* [GlobalISel] Lower integer operations to libcallsRichard-Qin-X2026-08-151-2/+9
* [RISCV] Match explicit target feature semanticsRichard-Qin-X2026-08-151-5/+14
* [GlobalISel] Lower integer rotate operationsRichard-Qin-X2026-08-151-0/+28
* [GlobalISel] Legalize constants and implicit definitionsRichard-Qin-X2026-08-151-34/+36
* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-151-4/+5
* [GlobalISel] Legalize G_ABDS and G_ABDURichard-Qin-X2026-08-143-178/+19
* [GlobalISel] Legalize G_ABSRichard-Qin-X2026-08-141-0/+86
* [RISCV] Legalize va_copy intrinsicsRichard-Qin-X2026-08-142-0/+122
* [GlobalISel] Match LLVM legalization value trackingRichard-Qin-X2026-08-142-1/+69
* [CodeGen] Match LLVM Legalizer ownershipRichard-Qin-X2026-08-143-3090/+410
* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-136-436/+457
* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-132-6/+342
* [CodeGen] Match LLVM branch relaxation semanticsRichard-Qin-X2026-08-132-1/+75
* [RISCV] Model non-ISA subtarget featuresRichard-Qin-X2026-08-131-7/+70
* [RISCV] Match LLVM register bank mappingsRichard-Qin-X2026-08-133-28/+266
* [RISCV] Preserve wide carry instruction orderRichard-Qin-X2026-08-131-10/+18
* [RISCV] Centralize legalizer register type queriesRichard-Qin-X2026-08-131-118/+97
* [RISCV] Remove physical register forwarding helpersRichard-Qin-X2026-08-133-57/+39
* [RISCV] Use the generated opcode conversionRichard-Qin-X2026-08-138-194/+164
* [TableGen] Split the target description generatorRichard-Qin-X2026-08-131-2/+2
* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-131-175/+43
* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-134-17/+15
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-131-10/+12
* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-131-3/+4
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-1222-6638/+6854
* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-122-14/+16
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-126-214/+140
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-121-2/+2
* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-121-14/+0
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-121-2/+11
* [RISCV] Describe vector tuple registersRichard-Qin-X2026-08-122-1/+87
* [RISCV] Describe vector physical registersRichard-Qin-X2026-08-121-0/+77
* [RISCV] Add Zba and Zbb instruction descriptionsRichard-Qin-X2026-08-123-2/+253
* [RISCV] Make call-preserved masks optionalRichard-Qin-X2026-08-121-2/+2
* [RISCV] Make target memory operands optionalRichard-Qin-X2026-08-122-53/+3
* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-121-2/+2
* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-121-0/+4
* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-121-3/+188
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 14:43:22 +0000