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* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-122-14/+16
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-126-214/+140
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-121-2/+2
* [Tooling] Remove the duplicate assembly emitterRichard-Qin-X2026-08-121-14/+0
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-121-2/+11
* [RISCV] Describe vector tuple registersRichard-Qin-X2026-08-122-1/+87
* [RISCV] Describe vector physical registersRichard-Qin-X2026-08-121-0/+77
* [RISCV] Add Zba and Zbb instruction descriptionsRichard-Qin-X2026-08-123-2/+253
* [RISCV] Make call-preserved masks optionalRichard-Qin-X2026-08-121-2/+2
* [RISCV] Make target memory operands optionalRichard-Qin-X2026-08-122-53/+3
* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-121-2/+2
* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-121-0/+4
* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-121-3/+188
* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-121-15/+15
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-0/+103
* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-121-1/+1
* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-121-0/+50
* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-122-0/+90
* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-0/+15
* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-0/+163
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-125-12/+44
* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-117-77/+183
* [RISCV] Order call operands like LLVM MIRRichard-Qin-X2026-08-111-8/+8
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-114-55/+97
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-114-20/+5
* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-114-74/+33
* [RISCV] Use canonical copies for full ABI valuesRichard-Qin-X2026-08-111-4/+10
* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-111-3/+123
* [RISCV] Accept generic scalars in call loweringRichard-Qin-X2026-08-111-3/+2
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-114-7/+130
* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-111-15/+49
* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-0/+18
* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+28
* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-4/+151
* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-2/+3
* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-111-0/+94
* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-111-2/+3
* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-111-0/+140
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-119-32/+2824
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-102-0/+166
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-098-34/+2004
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-094-1/+1522
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0910-36/+1697
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-093-0/+2106
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-095-24/+311
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-081-0/+199
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-082-0/+3243
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-072-0/+1477
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-075-15/+4969
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-076-0/+1589
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 13:25:25 +0000