| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [MC] Implement RV64GC assembly emission | Richard-Qin-X | 2026-08-09 | 4 | -1/+1522 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 10 | -36/+1697 |
| * | [CodeGen] Implement RV64GC frame lowering | Richard-Qin-X | 2026-08-09 | 3 | -0/+2106 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 5 | -24/+311 |
| * | [CodeGen] Implement machine SSA exit | Richard-Qin-X | 2026-08-08 | 1 | -0/+199 |
| * | [CodeGen] Implement RV64GC legalization and instruction selection | Richard-Qin-X | 2026-08-08 | 2 | -0/+3243 |
| * | [CodeGen] Complete machine pass and ABI lowering infrastructure | Richard-Qin-X | 2026-08-07 | 2 | -0/+1477 |
| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 5 | -15/+4969 |
| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 6 | -0/+1589 |
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