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Commit message (Collapse)AuthorAgeFilesLines
* [CMake] Remove unused clang-tidy file registrationRichard-Qin-X2026-08-281-9/+0
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* [CodeGen] Add target machine registryRichard-Qin-X2026-08-285-135/+120
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* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-261-2/+11
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* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-251-3/+64
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* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-241-2/+5
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* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-242-5/+16
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* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-221-0/+8
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* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-221-2/+23
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* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-192-2/+2
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* [RISCV][GlobalISel] Legalize floating-point remainderRichard-Qin-X2026-08-151-2/+13
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* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-151-4/+6
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* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-131-1/+1
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* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-131-2/+10
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* [Tooling] Avoid unchecked pipeline selectorsRichard-Qin-X2026-08-131-3/+2
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* [Tooling] Remove the duplicate output kindRichard-Qin-X2026-08-134-118/+66
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* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-134-4/+4
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* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-131-4/+4
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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-122-15/+23
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* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-124-124/+117
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* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-122-6/+9
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* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-124-5/+0
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* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-111-10/+17
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* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-111-0/+2
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* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-108-0/+3638