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path: root/backend/unittests/CodeGen/TargetRegisterInfoTest.cpp
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* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-131-2/+2
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* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-091-0/+6
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* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-071-0/+13
| | | | Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-011-0/+359
Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.