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* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-152-79/+48
* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-1322-189/+142
* [RISCV] Match LLVM register bank mappingsRichard-Qin-X2026-08-131-12/+9
* [CodeGen] Avoid unchecked memory alignment accessRichard-Qin-X2026-08-131-2/+2
* [CodeGen] Inline liveness test helpersRichard-Qin-X2026-08-131-16/+16
* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-137-26/+25
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-1321-1001/+975
* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-1314-990/+1195
* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-135-1186/+1220
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-127-19/+40
* [GlobalISel] Split the generic pipeline componentsRichard-Qin-X2026-08-127-703/+810
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-121-15/+56
* [CodeGen] Verify local physical live-insRichard-Qin-X2026-08-121-0/+30
* [CodeGen] Allow dynamic implicit operands on copiesRichard-Qin-X2026-08-121-0/+5
* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-121-1/+0
* [CodeGen] Allow narrow atomic RMW memory typesRichard-Qin-X2026-08-121-0/+25
* [CodeGen] Preserve variable-sized stack object offsetsRichard-Qin-X2026-08-121-0/+6
* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-121-13/+7
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-3/+6
* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-121-3/+25
* [CodeGen] Test cloning unnamed functionsRichard-Qin-X2026-08-121-5/+5
* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-121-1/+12
* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-111-0/+41
* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-111-0/+6
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-111-1/+0
* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-0/+61
* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-111-0/+5
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-111-1/+25
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-114-16/+86
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-091-3/+29
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-091-2/+42
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-095-0/+1365
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-091-2/+10
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0911-2/+2364
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-094-18/+936
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-084-3/+1350
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-082-0/+643
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-075-0/+2473
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-071-0/+13
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-076-12/+18
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-041-6/+28
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-034-8/+406
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-032-0/+497
* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-025-24/+335
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-022-0/+226
* [CodeGen] Track debug instruction identitiesRichard-Qin-X2026-08-012-0/+283
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-012-0/+337
* [CodeGen] Add MIR function and block attributesRichard-Qin-X2026-08-012-0/+221
* [MIR] Add compilation unit reference contextRichard-Qin-X2026-08-012-0/+70
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-017-109/+1000
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 10:57:57 +0000