rcc-project - An optimizing compiler for C.

	Commit message (Collapse)	Author	Age	Files	Lines
*	[RISCV] Allow frame indices in ADDI	Richard-Qin-X	2026-08-12	1	-4/+5
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*	[RISCV] Model dynamic rounding-mode state	Richard-Qin-X	2026-08-12	1	-7/+15
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*	[RISCV] Model FFLAGS accesses	Richard-Qin-X	2026-08-12	1	-4/+11
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*	[RISCV] Describe the GPR select pseudo	Richard-Qin-X	2026-08-12	1	-1/+1
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*	[RISCV] Model target-specific generic opcodes	Richard-Qin-X	2026-08-12	1	-1/+1
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*	[RISCV] Support absolute address operand flags	Richard-Qin-X	2026-08-12	1	-3/+5
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*	[RISCV] Model typed floating-point register views	Richard-Qin-X	2026-08-11	1	-13/+27
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*	[RISCV] Add LP64 calling-convention facts	Richard-Qin-X	2026-08-11	1	-10/+20
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*	[RISCV] Derive the generated instruction count in tests	Richard-Qin-X	2026-08-11	1	-1/+5
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*	[CodeGen] Implement machine optimization and scheduling	Richard-Qin-X	2026-08-09	1	-2/+2
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*	[RISCV] Complete RV64GC instruction description	Richard-Qin-X	2026-08-07	1	-2/+95
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*	[RISCV] Add generated RV64GC register description	Richard-Qin-X	2026-08-07	1	-0/+109
	Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.