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* [RISCV] Use the generated opcode conversionRichard-Qin-X2026-08-132-25/+30
* [TableGen] Split the target description generatorRichard-Qin-X2026-08-132-10/+7
* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-134-8/+8
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-134-34/+34
* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-133-3/+4
* [CodeGen] Split PHI elimination and two-address rewritingRichard-Qin-X2026-08-131-1/+1
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-127-201/+171
* [RISCV] Consolidate instruction behavior in RISCVInstrInfoRichard-Qin-X2026-08-123-35/+113
* [CodeGen] Add TargetInstrInfo ownershipRichard-Qin-X2026-08-121-1/+1
* [RISCV] Describe vector tuple registersRichard-Qin-X2026-08-121-2/+13
* [RISCV] Describe vector physical registersRichard-Qin-X2026-08-121-3/+12
* [RISCV] Add Zba and Zbb instruction descriptionsRichard-Qin-X2026-08-123-6/+39
* [RISCV] Make call-preserved masks optionalRichard-Qin-X2026-08-121-1/+5
* [RISCV] Make target memory operands optionalRichard-Qin-X2026-08-121-2/+12
* [RISCV] Legalize G_PTR_ADD with s64 offsetsRichard-Qin-X2026-08-121-0/+27
* [RISCV] Legalize G_FRAME_INDEX for p0Richard-Qin-X2026-08-121-0/+50
* [RISCV] Legalize G_VAARGRichard-Qin-X2026-08-121-0/+89
* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-121-0/+32
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-121-0/+81
* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-121-4/+5
* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-121-7/+15
* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-122-6/+29
* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-1/+1
* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-1/+1
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-122-3/+51
* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-117-78/+120
* [RISCV] Order call operands like LLVM MIRRichard-Qin-X2026-08-111-7/+20
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-114-13/+47
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-113-9/+4
* [RISCV] Derive the generated instruction count in testsRichard-Qin-X2026-08-111-1/+5
* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-112-11/+47
* [RISCV] Use canonical copies for full ABI valuesRichard-Qin-X2026-08-111-3/+5
* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-111-0/+59
* [RISCV] Accept generic scalars in call loweringRichard-Qin-X2026-08-111-0/+16
* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-111-0/+69
* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-3/+20
* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+43
* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-16/+53
* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-0/+49
* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-111-1/+37
* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-111-0/+37
* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-111-0/+86
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-114-6/+6
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-101-1/+2
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-096-1/+1509
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-095-0/+235
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-094-3/+1448
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-093-0/+1416
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-093-16/+521
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-091-2/+11
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 12:03:33 +0000