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* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-111-0/+59
* [RISCV] Accept generic scalars in call loweringRichard-Qin-X2026-08-111-0/+16
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-111-0/+19
* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-111-0/+69
* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-0/+61
* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-3/+20
* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+43
* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-16/+53
* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-0/+49
* [MIR] Omit absent zero-offset MMO basesRichard-Qin-X2026-08-111-2/+9
* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-111-1/+37
* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-111-0/+37
* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-111-0/+86
* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-112-9/+52
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-115-7/+31
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-1112-21/+318
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1011-1/+1195
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-0910-6/+2060
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-0910-2/+436
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0910-3/+2823
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-095-2/+1428
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0914-18/+2885
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-096-21/+949
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-086-3/+1703
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-084-0/+1758
* [CodeGen] Complete machine pass and ABI lowering infrastructureRichard-Qin-X2026-08-077-0/+3282
* [RISCV] Complete RV64GC instruction descriptionRichard-Qin-X2026-08-072-23/+199
* [RISCV] Add generated RV64GC register descriptionRichard-Qin-X2026-08-075-2/+262
* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-0711-14/+1566
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-043-6/+437
* [MIR] Add machine instruction lexerRichard-Qin-X2026-08-032-2/+431
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-036-9/+448
* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-032-0/+497
* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-025-24/+335
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-022-0/+226
* [CodeGen] Track debug instruction identitiesRichard-Qin-X2026-08-012-0/+283
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-012-0/+337
* [CodeGen] Add MIR function and block attributesRichard-Qin-X2026-08-012-0/+221
* [MIR] Add compilation unit reference contextRichard-Qin-X2026-08-015-0/+214
* [Support] Add MIR YAML parsing infrastructureRichard-Qin-X2026-08-013-3/+292
* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-0111-109/+1259
* [CodeGen] Add target state and compilation statusRichard-Qin-X2026-08-015-0/+666
* [CodeGen] Add constant and jump table stateRichard-Qin-X2026-08-017-26/+1043
* [CodeGen] Add MachineFrameInfoRichard-Qin-X2026-08-015-15/+294
* [CodeGen] Add explicit MachineFunction cloningRichard-Qin-X2026-08-012-0/+459
* [CodeGen] Add strict MachineIR verificationRichard-Qin-X2026-08-012-0/+474
* [CodeGen] Add transactional MachineIR builderRichard-Qin-X2026-08-012-0/+477
* [CodeGen] Add machine instruction descriptorsRichard-Qin-X2026-08-012-0/+376
* [CodeGen] Build the core MachineIR object modelRichard-Qin-X2026-08-012-0/+479
* [CodeGen] Add machine IR value semanticsRichard-Qin-X2026-08-012-5/+207
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 10:04:31 +0000