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* [RISCV] Accept symbolic low operands in loads and storesRichard-Qin-X2026-08-121-0/+32
* [RISCV] Legalize llvm.va_copyRichard-Qin-X2026-08-122-3/+87
* [RISCV] Allow frame indices in ADDIRichard-Qin-X2026-08-121-4/+5
* [MIR] Create virtual registers referenced by live-insRichard-Qin-X2026-08-121-0/+43
* [CodeGen] Track reserved register defs preciselyRichard-Qin-X2026-08-121-3/+25
* [CodeGen] Test cloning unnamed functionsRichard-Qin-X2026-08-121-5/+5
* [RISCV] Model dynamic rounding-mode stateRichard-Qin-X2026-08-121-7/+15
* [RISCV] Model FFLAGS accessesRichard-Qin-X2026-08-122-6/+29
* [MIR] Ignore empty YAML documentsRichard-Qin-X2026-08-121-0/+31
* [RISCV] Describe the GPR select pseudoRichard-Qin-X2026-08-121-1/+1
* [CodeGen] Accept pointer comparisons in G_ICMPRichard-Qin-X2026-08-121-1/+12
* [RISCV] Model target-specific generic opcodesRichard-Qin-X2026-08-121-1/+1
* [RISCV] Support absolute address operand flagsRichard-Qin-X2026-08-122-3/+51
* [MIR] Accept physical-only function live-insRichard-Qin-X2026-08-121-2/+3
* [MIR] Accept unnamed stack objectsRichard-Qin-X2026-08-121-1/+2
* [MIR] Accept empty optional register fieldsRichard-Qin-X2026-08-121-2/+3
* [CodeGen] Treat reserved registers as always liveRichard-Qin-X2026-08-111-0/+41
* [CodeGen] Accept conservative physical live-insRichard-Qin-X2026-08-111-0/+6
* [RISCV] Model typed floating-point register viewsRichard-Qin-X2026-08-117-78/+120
* [RISCV] Order call operands like LLVM MIRRichard-Qin-X2026-08-111-7/+20
* [RISCV] Add LP64 calling-convention factsRichard-Qin-X2026-08-114-13/+47
* [CodeGen] Remove redundant numeric call-site IDsRichard-Qin-X2026-08-114-10/+4
* [RISCV] Derive the generated instruction count in testsRichard-Qin-X2026-08-111-1/+5
* [RISCV] Match LLVM call-frame pseudo semanticsRichard-Qin-X2026-08-112-11/+47
* [RISCV] Use canonical copies for full ABI valuesRichard-Qin-X2026-08-111-3/+5
* [RISCV] Lower multiply without M through libcallsRichard-Qin-X2026-08-111-0/+59
* [RISCV] Accept generic scalars in call loweringRichard-Qin-X2026-08-111-0/+16
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-111-0/+19
* [RISCV] Fold narrow binary artifact chainsRichard-Qin-X2026-08-111-0/+69
* [CodeGen] Revisit instructions invalidated by legalizationRichard-Qin-X2026-08-111-0/+61
* [RISCV] Preserve folded constant placementRichard-Qin-X2026-08-111-3/+20
* [RISCV] Reuse compare operand extensionsRichard-Qin-X2026-08-111-0/+43
* [RISCV] Legalize integer compares to RV64 containersRichard-Qin-X2026-08-111-16/+53
* [RISCV] Preserve live constants when folding extensionsRichard-Qin-X2026-08-111-0/+49
* [MIR] Omit absent zero-offset MMO basesRichard-Qin-X2026-08-111-2/+9
* [RISCV] Lower cmpxchg with successRichard-Qin-X2026-08-111-1/+37
* [RISCV] Preserve narrow cmpxchg results when wideningRichard-Qin-X2026-08-111-0/+37
* [RISCV] Legalize narrow atomic compare exchangeRichard-Qin-X2026-08-111-0/+86
* [MIR] Parse one-ordering compare-exchange MMOsRichard-Qin-X2026-08-112-9/+52
* [RISCV] Legalize fixed-baseline RV64 MachineIRRichard-Qin-X2026-08-115-7/+31
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-1112-21/+318
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-1011-1/+1195
* [MC] Implement RV64GC object emissionRichard-Qin-X2026-08-0910-6/+2060
* [MC] Implement RV64GC assembly emissionRichard-Qin-X2026-08-0910-2/+436
* [CodeGen] Implement machine optimization and schedulingRichard-Qin-X2026-08-0910-3/+2823
* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-095-2/+1428
* [CodeGen] Complete register allocation infrastructureRichard-Qin-X2026-08-0914-18/+2885
* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-096-21/+949
* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-086-3/+1703
* [CodeGen] Implement RV64GC legalization and instruction selectionRichard-Qin-X2026-08-084-0/+1758
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 12:09:21 +0000