| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | refactor(core): address WB stage architectural and naming review feedback | Richard Qin | 2026-03-17 | 1 | -12/+17 |
| * | Write Back stage unit and tests | Richard Qin | 2026-03-18 | 1 | -0/+116 |
| * | docs: Finalized Richard CPU RTL architectural and naming convention audit rep... | Richard Qin | 2026-03-17 | 7 | -17/+595 |
| * | Execute Stage unit and tests | Richard Qin | 2026-03-17 | 1 | -0/+114 |
| * | ID/EX Pipeline Register and tests | Richard Qin | 2026-03-17 | 1 | -0/+174 |
| * | IF/ID RegFile and tests | Richard Qin | 2026-03-17 | 1 | -0/+57 |
| * | Instruction Decoder Stage unit and tests | Richard Qin | 2026-03-17 | 1 | -0/+142 |
| * | Instruction fetching stage unit and test | Richard Qin | 2026-03-16 | 1 | -0/+60 |
| * | branch unit and test | Richard Qin | 2026-03-16 | 2 | -0/+65 |
| * | fix naming problems | Richard Qin | 2026-03-16 | 3 | -39/+39 |
| * | Decoder unit and test | Richard Qin | 2026-03-16 | 1 | -0/+390 |
| * | Register file unit and test | Richard Qin | 2026-03-16 | 1 | -0/+60 |
| * | Add and test alu unit | Richard Qin | 2026-03-15 | 2 | -0/+160 |
| * | initial commit: project architecture | Richard Qin | 2026-03-15 | 10 | -0/+0 |
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