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* build: reorganize CMake configurationRichard Qin3 days1-0/+44
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* refactor: align RTL module names with filesRichard Qin3 days10-15/+15
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* refactor: rename RTL source filesRichard Qin3 days8-0/+0
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* refactor: reorganize RTL directory structureRichard Qin3 days31-0/+0
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* checkpoint: preserve current RV64 CPU development stateRichard Qin3 days24-456/+6344
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* refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-071-5/+5
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* refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-074-66/+66
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* feat(tlb): enhance TLB functionality with ASID-targeted flush and additional ↵Richard Qin2026-04-071-1/+1
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* feat(tlb): add parameterized L1 TLB module and corresponding unit testsRichard Qin2026-04-011-0/+378
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* feat: Complete CSR/privileged/exception interrupt path and fill in strict ↵Richard Qin2026-04-0111-135/+410
| | | | | | | | | | | | | | | | | acceptance tests - Refactor trap/CSR data path in the Core, unified with trap_ctrl interface to drive CSR update and return process - Improve critical paths for exception/interrupt handling: ecall, illegal, load fault, external interrupt, mret/sret return - Adjust pipeline stage registers with flush/stall coordination, fix residual control signal issues in trap scenarios - Enhance decode and related pipeline module behavior consistency, fill in missing control signal propagation across registers - Expand core integration testing, add trap/interrupt scenarios and CLI dispatch that can be executed per case - Extend CSR unit test coverage: read/write semantics, privilege switching, delegation and nested returns, illegal access protection, etc. - Register new core scenario cases in CTest to form a regression-capable P2 strict acceptance suite Verification: - Build passed - Full CTest passed (22/22)
* Trap Control unit and testsRichard Qin2026-03-191-0/+204
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* CSR unit and testsRichard Qin2026-03-193-1/+547
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* M/S/U Mode csr pakageRichard Qin2026-03-181-0/+110
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* Add fibonacci tests and fix bugsRichard Qin2026-03-181-2/+9
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* CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-181-0/+556
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* Hazard unit and testsRichard Qin2026-03-181-0/+152
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* refactor(core): address WB stage architectural and naming review feedbackRichard Qin2026-03-171-12/+17
| | | | | | | | - Renamed `wb_reg_write_data` and `wb_reg_write_addr` to `wb_rd_wdata` and `wb_rd_addr` respectively to comply with `docs/naming_convention.md`. - Removed the 64-bit adder for `mem_wb_pc + 64'd4` from the WB stage to improve timing. Introduced a new `mem_wb_pc_plus_4` pipeline input instead. - Added a `has_trap` signal to gate architectural state updates (`wb_reg_write_en` and `csr_req`) upon exceptions, ensuring precise exceptions without corrupting the register file or CSRs. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* Write Back stage unit and testsRichard Qin2026-03-181-0/+116
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* docs: Finalized Richard CPU RTL architectural and naming convention audit ↵Richard Qin2026-03-177-17/+595
| | | | | | | | report. No source code changes were made; this branch serves as the finalized state for the provided audit. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* Execute Stage unit and testsRichard Qin2026-03-171-0/+114
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* ID/EX Pipeline Register and testsRichard Qin2026-03-171-0/+174
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* IF/ID RegFile and testsRichard Qin2026-03-171-0/+57
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* Instruction Decoder Stage unit and testsRichard Qin2026-03-171-0/+142
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* Instruction fetching stage unit and testRichard Qin2026-03-161-0/+60
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* branch unit and testRichard Qin2026-03-162-0/+65
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* fix naming problemsRichard Qin2026-03-163-39/+39
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* Decoder unit and testRichard Qin2026-03-161-0/+390
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* Register file unit and testRichard Qin2026-03-161-0/+60
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* Add and test alu unitRichard Qin2026-03-152-0/+160
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* initial commit: project architectureRichard Qin2026-03-1510-0/+0
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