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Added a specific test scenario for Store Page Fault in tb/unit/tb_trap_ctrl.cc.
- Defined EXC_STORE_PAGE_FAULT (15) constant.
- Implemented a test case that asserts trap_store_page_fault and verifies mcause and mtval.
- Improved clarity by renaming existing page fault test labels to LoadPageFault.
Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
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acceptance tests
- Refactor trap/CSR data path in the Core, unified with trap_ctrl interface to drive CSR update and return process
- Improve critical paths for exception/interrupt handling: ecall, illegal, load fault, external interrupt, mret/sret return
- Adjust pipeline stage registers with flush/stall coordination, fix residual control signal issues in trap scenarios
- Enhance decode and related pipeline module behavior consistency, fill in missing control signal propagation across registers
- Expand core integration testing, add trap/interrupt scenarios and CLI dispatch that can be executed per case
- Extend CSR unit test coverage: read/write semantics, privilege switching, delegation and nested returns, illegal access protection, etc.
- Register new core scenario cases in CTest to form a regression-capable P2 strict acceptance suite
Verification:
- Build passed
- Full CTest passed (22/22)
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- Renamed `wb_reg_write_data` to `wb_rd_wdata` in all assertions to match the updated module ports.
- Renamed `wb_reg_write_addr` to `wb_rd_addr` in all assertions.
- Initialized the new `mem_wb_pc_plus_4` input in the testbench setup to correctly test the JAL/JALR datapath.
- Added assertions to explicitly test that `wb_reg_write_en` and `csr_req` are gated when an exception occurs.
Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
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- Renamed `wb_reg_write_data` and `wb_reg_write_addr` to `wb_rd_wdata` and `wb_rd_addr` respectively to comply with `docs/naming_convention.md`.
- Removed the 64-bit adder for `mem_wb_pc + 64'd4` from the WB stage to improve timing. Introduced a new `mem_wb_pc_plus_4` pipeline input instead.
- Added a `has_trap` signal to gate architectural state updates (`wb_reg_write_en` and `csr_req`) upon exceptions, ensuring precise exceptions without corrupting the register file or CSRs.
Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
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report.
No source code changes were made; this branch serves as the finalized state for the provided audit.
Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
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