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* fixed vm_trace bugRichard Qin2026-03-181-6/+6
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* CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-185-8/+1252
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* Hazard unit and testsRichard Qin2026-03-183-0/+446
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* test(core): fix WB stage tests after naming and logic refactorRichard Qin2026-03-171-5/+8
| | | | | | | | | - Renamed `wb_reg_write_data` to `wb_rd_wdata` in all assertions to match the updated module ports. - Renamed `wb_reg_write_addr` to `wb_rd_addr` in all assertions. - Initialized the new `mem_wb_pc_plus_4` input in the testbench setup to correctly test the JAL/JALR datapath. - Added assertions to explicitly test that `wb_reg_write_en` and `csr_req` are gated when an exception occurs. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* refactor(core): address WB stage architectural and naming review feedbackRichard Qin2026-03-171-12/+17
| | | | | | | | - Renamed `wb_reg_write_data` and `wb_reg_write_addr` to `wb_rd_wdata` and `wb_rd_addr` respectively to comply with `docs/naming_convention.md`. - Removed the 64-bit adder for `mem_wb_pc + 64'd4` from the WB stage to improve timing. Introduced a new `mem_wb_pc_plus_4` pipeline input instead. - Added a `has_trap` signal to gate architectural state updates (`wb_reg_write_en` and `csr_req`) upon exceptions, ensuring precise exceptions without corrupting the register file or CSRs. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* Write Back stage unit and testsRichard Qin2026-03-183-0/+240
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* docs: Finalized Richard CPU RTL architectural and naming convention audit ↵Richard Qin2026-03-1713-20/+1190
| | | | | | | | report. No source code changes were made; this branch serves as the finalized state for the provided audit. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
* Execute Stage unit and testsRichard Qin2026-03-173-0/+343
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* ID/EX Pipeline Register and testsRichard Qin2026-03-173-0/+354
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* IF/ID RegFile and testsRichard Qin2026-03-173-0/+193
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* Instruction Decoder Stage unit and testsRichard Qin2026-03-173-0/+345
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* Instruction fetching stage unit and testRichard Qin2026-03-163-0/+180
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* branch unit and testRichard Qin2026-03-164-0/+174
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* format outputRichard Qin2026-03-163-13/+20
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* expand tests and format outputRichard Qin2026-03-163-9/+124
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* fix naming problemsRichard Qin2026-03-167-84/+77
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* Naming conventionRichard Qin2026-03-161-0/+159
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* Decoder unit and testRichard Qin2026-03-163-9/+697
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* Register file unit and testRichard Qin2026-03-163-13/+172
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* LicenseRichard Qin2026-03-151-0/+17
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* Add and test alu unitRichard Qin2026-03-156-8/+241
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* initial commit: project architectureRichard Qin2026-03-1541-0/+2185
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