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authorRichard Qin <richard.qin.x@gmail.com>2026-04-21 23:05:54 +0800
committerRichard Qin <richard.qin.x@gmail.com>2026-04-21 23:05:54 +0800
commitb0ccdda4bc3af04e54677cd910ed04c5ba1b1a63 (patch)
tree2e5e065ea30abf6e07fc3f8ebf5a653dd5c2849e /na/arch/riscv/include
parentdf1af31b90d904fddc45c6da6da5ee36d905a0ca (diff)
downloadlume-b0ccdda4bc3af04e54677cd910ed04c5ba1b1a63.tar.gz
lume-b0ccdda4bc3af04e54677cd910ed04c5ba1b1a63.tar.xz
feat: add RISC-V architecture configuration header with memory layout constants
Diffstat (limited to 'na/arch/riscv/include')
-rw-r--r--na/arch/riscv/include/arch/config.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/na/arch/riscv/include/arch/config.h b/na/arch/riscv/include/arch/config.h
new file mode 100644
index 0000000..2a70f2a
--- /dev/null
+++ b/na/arch/riscv/include/arch/config.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright (C) 2026 Richard Qin */
+
+#pragma once
+
+/*
+ * RISC-V Architecture Configuration
+ *
+ * These constants define the architecture-specific memory layout.
+ * Each arch/ implementation must provide this header with the same symbols.
+ */
+
+#include <lume/types.h>
+
+namespace arch {
+
+/* Kernel virtual address offset (higher-half base).
+ * SV39: top of 39-bit VA space. VA = PA + kVAOffset. */
+inline constexpr uint64 kVAOffset = 0xFFFFFFC000000000ULL;
+
+/* Physical memory base (where RAM starts on RISC-V virt platform) */
+inline constexpr uint64 kPhysBase = 0x80000000ULL;
+
+/* Platform default MMIO base addresses (QEMU virt) */
+inline constexpr uint64 kDefaultUartPA = 0x10000000ULL;
+inline constexpr uint64 kDefaultPlicPA = 0x0C000000ULL;
+
+} // namespace arch