[RISCV] Consolidate instruction behavior in RISCVInstrInfo

1 files changed, 1 insertions, 3 deletions

diff --git a/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h b/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h
index 2cf1bcd..10bcbc6 100644
--- a/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h
+++ b/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h
@@ -13,16 +13,14 @@ class TargetMachineCombinerInfo;
 class TargetMemoryFoldingInfo;
 class TargetPseudoExpansionInfo;
 class TargetSchedulingModel;
-class TargetSSAInfo;
 
 struct MachineOptimizationPipelineTargetInfo final {
-  const TargetSSAInfo &SSA;
+  const TargetInstrInfo &InstrInfo;
   const TargetMachineCombinerInfo &Combiner;
   const TargetMemoryFoldingInfo &MemoryFolding;
   const TargetFrameLowering &FrameLowering;
   const TargetPseudoExpansionInfo &PseudoExpansion;
   const TargetSchedulingModel &SchedulingModel;
-  const TargetInstrInfo &BranchInfo;
 };
 
 [[nodiscard]] Expected<void> registerMachineOptimizationAnalyses(MachineAnalysisManager &Analyses);