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| author | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-25 03:11:23 +0800 |
|---|---|---|
| committer | Richard-Qin-X <richard.qin.001@gmail.com> | 2026-08-25 03:11:23 +0800 |
| commit | f5d9ddc085055d28d6f9fb3730c3566097f43fb2 (patch) | |
| tree | d1ca89a409a0d1a167e79e3d1693c22bcfd823a9 /backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp | |
| parent | c3932f55208e3fe2019d26a0e5af421c0b644872 (diff) | |
| download | rcc-project-f5d9ddc085055d28d6f9fb3730c3566097f43fb2.tar.gz rcc-project-f5d9ddc085055d28d6f9fb3730c3566097f43fb2.tar.xz | |
[CodeGen] Implement the greedy register allocator pipeline
Diffstat (limited to 'backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp')
| -rw-r--r-- | backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp index 99c261c..2b34f53 100644 --- a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp +++ b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp @@ -60,10 +60,14 @@ createStackMemoryOperand(MachineIRBuilder &Builder, FrameIndex StackSlot, Memory auto Align = Alignment::create(AlignmentInBytes); if (!Align) return std::unexpected(Align.error()); + auto Type = LowLevelType::makeCategoryNeutralScalar(SizeInBytes * 8U); + if (!Type) + return std::unexpected(Type.error()); MachineMemOperandDesc Description; Description.Accesses = {Access}; Description.Size = *Size; + Description.MemoryType = *Type; Description.Align = *Align; Description.Base = MemoryBase::frameIndex(StackSlot); return Builder.function().createMemOperand(std::move(Description)); |