refactor: align RTL module names with files

1 files changed, 1 insertions, 1 deletions

diff --git a/rv64cpu/rtl/core/execute/instruction_decoder.sv b/rv64cpu/rtl/core/execute/instruction_decoder.sv
index c39a637..14d9559 100644
--- a/rv64cpu/rtl/core/execute/instruction_decoder.sv
+++ b/rv64cpu/rtl/core/execute/instruction_decoder.sv
@@ -19,7 +19,7 @@
 //              Translates 32-bit instructions into control signals for the pipeline.
 //              C is handled by the IF-stage decompressor before this decoder.
 
-module decoder
+module instruction_decoder
     import rv64_pkg::*;
 (
     input  logic [31:0]       instr,          // 32-bit instruction