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* [mubios] Implement INT 13h AH=41hRichard Qin46 hours2-0/+38
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Implement a minimal INT 10h AH=0EhRichard Qin46 hours2-0/+94
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Transfer control from the BIOS to the MBR, which has been loaded at ↵Richard Qin46 hours1-0/+18
| | | | | | 0x7C00. Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Add ATARichard Qin46 hours4-1/+115
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] fixed memory addressRichard Qin46 hours1-1/+1
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Have IRQ0 maintain the BIOS clock, and implement INT 1Ah AH=00h.Richard Qin47 hours3-0/+82
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Enable IRQ0Richard Qin47 hours7-19/+112
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Transition from protected mode back to real modeRichard Qin48 hours1-0/+74
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Create 16-bit entry points for IRQ0/IRQ1 and install the IVT vectors.Richard Qin2 days5-1/+92
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Fix the link order for the 16-bit entriesRichard Qin2 days3-3/+11
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Implement the PIC and PIT.Richard Qin2 days4-1/+117
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Implement the COM1 serial port driver and POST output.Richard Qin2 days4-0/+151
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Add Clangd SupportRichard Qin2 days2-1/+5
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Initialize IVT, BDA and EBDA.Richard Qin2 days4-2/+116
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Add Clang Format based on GNU styleRichard Qin2 days2-1/+5
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Add CFLAGS to close Exception Unwinding and Stack Unwinding MechanismRichard Qin2 days1-1/+2
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Building a 32-bit C entry in protected modeRichard Qin2 days4-0/+58
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Implement the switch from 16-bit to 32-bit protected modeRichard Qin2 days2-0/+112
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] Write mubios reset entry pointRichard Qin2 days2-1/+63
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [mubios] setup Makefile and linker scriptRichard Qin2 days3-0/+153
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [Tests] Remove LLVM testsRichard Qin2 days464-119059/+0
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [Doc] Move README to plain textRichard Qin3 days1-0/+0
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* [Doc] Update READMERichard Qin3 days1-34/+26
| | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
* Merge remote-tracking branch 'rv64cpu-import/master'Richard Qin3 days40-0/+11937
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| * chore: update ignore rulesRichard Qin3 days1-17/+41
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| * build: reorganize CMake configurationRichard Qin3 days2-42/+55
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| * refactor: update READMERichard Qin3 days1-139/+5
| | | | | | | | Signed-off-by: Richard Qin <richard.qin.x@gmail.com>
| * refactor: rename documentsRichard Qin3 days2-0/+0
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| * chore: remove obsolete toolingRichard Qin3 days3-503/+0
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| * refactor: reset software and test directoriesRichard Qin3 days27-6731/+0
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| * refactor: align RTL module names with filesRichard Qin3 days10-15/+15
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| * refactor: rename RTL source filesRichard Qin3 days8-0/+0
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| * refactor: reorganize RTL directory structureRichard Qin3 days44-0/+0
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| * checkpoint: preserve current RV64 CPU development stateRichard Qin3 days38-911/+7735
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| * refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-074-36/+36
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| * refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-079-90/+135
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| * feat(tlb): enhance TLB functionality with ASID-targeted flush and additional ↵Richard Qin2026-04-073-1/+70
| | | | | | | | test cases
| * feat(tlb): add parameterized L1 TLB module and corresponding unit testsRichard Qin2026-04-013-0/+805
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| * docs: update README and ISA support matrix with new dependencies and ↵Richard Qin2026-04-012-17/+50
| | | | | | | | compliance status
| * feat(compliance): implement ACT4 strict compliance flow with ELF runnerRichard Qin2026-04-014-72/+756
| | | | | | | | add functional compliance_runner with ELF loading, memory model, symbol-based signature dump, and tohost handling; wire compliance subdir/target in CMake; upgrade run_compliance.py for ACT4 suite mapping, robust binary/reference discovery, strict signature comparison, and aggregate suites (rv64g/rv64full).
| * feat: Add riscv-arch-test submodule for RISC-V architecture testingRichard Qin2026-04-012-0/+3
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| * Merge pull request #5 from ↵Richard Qin2026-04-011-2/+10
| |\ | | | | | | | | | | | | Richard-Qin-001/testing-improvement-store-page-fault-17466277746563964545 🧪 [trap_ctrl] add store page fault test case
| | * test(trap_ctrl): add store page fault unit test caseRichard Qin2026-03-311-2/+10
| |/ | | | | | | | | | | | | | | | | Added a specific test scenario for Store Page Fault in tb/unit/tb_trap_ctrl.cc. - Defined EXC_STORE_PAGE_FAULT (15) constant. - Implemented a test case that asserts trap_store_page_fault and verifies mcause and mtval. - Improved clarity by renaming existing page fault test labels to LoadPageFault. Co-authored-by: Richard-Qin-001 <69390919+Richard-Qin-001@users.noreply.github.com>
| * feat: Complete CSR/privileged/exception interrupt path and fill in strict ↵Richard Qin2026-04-0119-201/+1269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | acceptance tests - Refactor trap/CSR data path in the Core, unified with trap_ctrl interface to drive CSR update and return process - Improve critical paths for exception/interrupt handling: ecall, illegal, load fault, external interrupt, mret/sret return - Adjust pipeline stage registers with flush/stall coordination, fix residual control signal issues in trap scenarios - Enhance decode and related pipeline module behavior consistency, fill in missing control signal propagation across registers - Expand core integration testing, add trap/interrupt scenarios and CLI dispatch that can be executed per case - Extend CSR unit test coverage: read/write semantics, privilege switching, delegation and nested returns, illegal access protection, etc. - Register new core scenario cases in CTest to form a regression-capable P2 strict acceptance suite Verification: - Build passed - Full CTest passed (22/22)
| * Trap Control unit and testsRichard Qin2026-03-193-0/+406
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| * Update the latest progressRichard Qin2026-03-191-3/+11
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| * CSR unit and testsRichard Qin2026-03-195-10/+893
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| * M/S/U Mode csr pakageRichard Qin2026-03-181-0/+110
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| * Add fibonacci tests and fix bugsRichard Qin2026-03-183-8/+77
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| * fixed vm_trace bugRichard Qin2026-03-181-6/+6
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