aboutsummaryrefslogtreecommitdiff
Commit message (Expand)AuthorAgeFilesLines
* [mubios] Write mubios reset entry pointRichard Qin38 hours2-1/+63
* [mubios] setup Makefile and linker scriptRichard Qin39 hours3-0/+153
* [Tests] Remove LLVM testsRichard Qin43 hours464-119059/+0
* [Doc] Move README to plain textRichard Qin2 days1-0/+0
* [Doc] Update READMERichard Qin2 days1-34/+26
* Merge remote-tracking branch 'rv64cpu-import/master'Richard Qin2 days40-0/+11937
|\
| * chore: update ignore rulesRichard Qin2 days1-17/+41
| * build: reorganize CMake configurationRichard Qin2 days2-42/+55
| * refactor: update READMERichard Qin2 days1-139/+5
| * refactor: rename documentsRichard Qin2 days2-0/+0
| * chore: remove obsolete toolingRichard Qin2 days3-503/+0
| * refactor: reset software and test directoriesRichard Qin2 days27-6731/+0
| * refactor: align RTL module names with filesRichard Qin2 days10-15/+15
| * refactor: rename RTL source filesRichard Qin2 days8-0/+0
| * refactor: reorganize RTL directory structureRichard Qin2 days44-0/+0
| * checkpoint: preserve current RV64 CPU development stateRichard Qin2 days38-911/+7735
| * refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-074-36/+36
| * refactor: standardize interrupt signal naming across the codebaseRichard Qin2026-04-079-90/+135
| * feat(tlb): enhance TLB functionality with ASID-targeted flush and additional ...Richard Qin2026-04-073-1/+70
| * feat(tlb): add parameterized L1 TLB module and corresponding unit testsRichard Qin2026-04-013-0/+805
| * docs: update README and ISA support matrix with new dependencies and complian...Richard Qin2026-04-012-17/+50
| * feat(compliance): implement ACT4 strict compliance flow with ELF runnerRichard Qin2026-04-014-72/+756
| * feat: Add riscv-arch-test submodule for RISC-V architecture testingRichard Qin2026-04-012-0/+3
| * Merge pull request #5 from Richard-Qin-001/testing-improvement-store-page-fau...Richard Qin2026-04-011-2/+10
| |\
| | * test(trap_ctrl): add store page fault unit test caseRichard Qin2026-03-311-2/+10
| |/
| * feat: Complete CSR/privileged/exception interrupt path and fill in strict acc...Richard Qin2026-04-0119-201/+1269
| * Trap Control unit and testsRichard Qin2026-03-193-0/+406
| * Update the latest progressRichard Qin2026-03-191-3/+11
| * CSR unit and testsRichard Qin2026-03-195-10/+893
| * M/S/U Mode csr pakageRichard Qin2026-03-181-0/+110
| * Add fibonacci tests and fix bugsRichard Qin2026-03-183-8/+77
| * fixed vm_trace bugRichard Qin2026-03-181-6/+6
| * CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-185-8/+1252
| * Hazard unit and testsRichard Qin2026-03-183-0/+446
| * Merge pull request #3 from Richard-Qin-001/fix/wb-stage-review-99385726772028...Richard Qin2026-03-182-17/+25
| |\
| | * test(core): fix WB stage tests after naming and logic refactorRichard Qin2026-03-171-5/+8
| | * refactor(core): address WB stage architectural and naming review feedbackRichard Qin2026-03-171-12/+17
| |/
| * Write Back stage unit and testsRichard Qin2026-03-183-0/+240
| * Merge pull request #2 from Richard-Qin-001/audit-report-fixes-180556562870443...Richard Qin2026-03-186-29/+29
| |\
| | * Merge branch 'main' into audit-report-fixes-18055656287044378367Richard Qin2026-03-180-0/+0
| | |\ | | |/ | |/|
| * | Memory Stage and MEM/WB pipeline stage registerRichard Qin2026-03-185-0/+739
| * | fix known bugsRichard Qin2026-03-176-21/+68
| * | EX/MEM Pipeline Register unit and testsRichard Qin2026-03-177-2/+386
| | * docs: Finalized Richard CPU RTL architectural and naming convention audit rep...Richard Qin2026-03-1713-20/+1190
| |/
| * Execute Stage unit and testsRichard Qin2026-03-173-0/+343
| * ID/EX Pipeline Register and testsRichard Qin2026-03-173-0/+354
| * IF/ID RegFile and testsRichard Qin2026-03-173-0/+193
| * Instruction Decoder Stage unit and testsRichard Qin2026-03-173-0/+345
| * Instruction fetching stage unit and testRichard Qin2026-03-163-0/+180
| * branch unit and testRichard Qin2026-03-164-0/+174
generated by cgit v1.2.3 (git 2.46.0) at 2026-11-09 06:05:35 +0000