| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [CodeGen] Unify scalar low-level types | Richard-Qin-X | 2026-08-13 | 1 | -3/+3 |
| * | [RISCV] Match LLVM register bank mappings | Richard-Qin-X | 2026-08-13 | 1 | -0/+1 |
| * | [MIR] Accept fixed-baseline LLVM syntax | Richard-Qin-X | 2026-08-11 | 1 | -0/+2 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -0/+1 |
| * | [CodeGen] Add target MIR text schema | Richard-Qin-X | 2026-08-03 | 1 | -0/+3 |
| * | [CodeGen] Add strict MachineIR verification | Richard-Qin-X | 2026-08-01 | 1 | -0/+4 |
| * | [CodeGen] Build the core MachineIR object model | Richard-Qin-X | 2026-08-01 | 1 | -0/+168 |
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