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path: root/backend/lib/CodeGen/MIRPrinter.cpp
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* [CodeGen] Implement the greedy register allocator pipelineRichard-Qin-X2026-08-251-1/+1
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* [RISCV] Match LLVM large call frame loweringRichard-Qin-X2026-08-241-1/+1
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* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-241-21/+3
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* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-221-1/+2
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* [MIR] Print target generic operand typesRichard-Qin-X2026-08-151-2/+2
| | | | Use the instruction descriptor's Generic flag when deduplicating LLT annotations so target-specific generic pseudos follow LLVM MIR spelling.
* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-131-45/+5
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* [MIR] Omit predictable successors in simplified outputRichard-Qin-X2026-08-131-6/+64
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* [CodeGen] Preserve LLT annotations on generic opcodesRichard-Qin-X2026-08-131-2/+3
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* [IR] Split LL parsing, assembly writing, and data layoutRichard-Qin-X2026-08-131-10/+9
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* [Support] Split APInt and APFloat ownershipRichard-Qin-X2026-08-131-2/+2
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* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-131-0/+3167