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path: root/backend/lib/CodeGen/MachineVerifier.cpp
Commit message (Collapse)AuthorAgeFilesLines
* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-241-1/+0
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* [RISCV][GlobalISel] Select constant operands as immediatesRichard-Qin-X2026-08-161-5/+13
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* [GlobalISel] Clear virtual register types after selectionRichard-Qin-X2026-08-151-2/+3
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* [RISCV][GlobalISel] Legalize floating-point remainderRichard-Qin-X2026-08-151-0/+2
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* [CodeGen] Unify scalar low-level typesRichard-Qin-X2026-08-131-2/+2
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* [CodeGen] Reuse register diagnostic formattingRichard-Qin-X2026-08-131-2/+1
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* [CodeGen] Split machine liveness componentsRichard-Qin-X2026-08-131-1/+1
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* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-121-1/+1
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* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-111-12/+46
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* [CodeGen] Implement RV64GC frame loweringRichard-Qin-X2026-08-091-0/+3
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* [CodeGen] Implement machine liveness analysisRichard-Qin-X2026-08-091-0/+6
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* [CodeGen] Implement machine SSA exitRichard-Qin-X2026-08-081-3/+84
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* [MIR] Complete document parsing and printingRichard-Qin-X2026-08-071-0/+30
| | | | Implement the single LLVM-compatible MIR document path with structured\nembedded-IR references, YAML mappings, constants, and deterministic printing.\n\nKeep pointer LLT widths DataLayout-derived, reject layout-dependent output\nwhen embedded IR is omitted, and record the fixed-baseline compatibility\ncontract and regression coverage.
* [MIR] Add machine instruction parser and printerRichard-Qin-X2026-08-041-0/+38
| | | | Parse MachineFunction bodies in two passes and serialize the same MachineIR model in complete or readable form. Extend instruction attachments and memory operands required by the fixed LLVM MIR grammar, and cover deterministic parse-print round trips.
* [CodeGen] Add target MIR text schemaRichard-Qin-X2026-08-031-1/+12
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* [CodeGen] Model complete MIR operandsRichard-Qin-X2026-08-031-0/+45
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* [CodeGen] Model machine debug metadataRichard-Qin-X2026-08-021-3/+22
| | | | Replace marker-based metadata operands with scoped references and inline DIExpression values. Add structured DILocation chains, instruction debug attachments, stack variable records, and entry values with unified verification, builder support, and deterministic cloning.
* [CodeGen] Add machine metadata graphsRichard-Qin-X2026-08-021-0/+3
| | | | Model ordered function-local metadata tuples with explicit embedded-IR and MachineFunction reference scopes. Preserve slot zero, distinct nodes, forward references, and cyclic graphs while verifying function-local closure and cloning the graph deterministically.
* [CodeGen] Track debug instruction identitiesRichard-Qin-X2026-08-011-0/+20
| | | | Add monotonic MIR debug instruction numbers and structured value substitutions. Verify live number uniqueness, meta-instruction exclusion, substitution graph integrity, and target subregister references while preserving debug identities during cloning.
* [CodeGen] Add machine function recordsRichard-Qin-X2026-08-011-0/+68
| | | | Represent callee-saved registers, call-site information, called globals, and prefetch targets in the core MachineIR model. Verify target and instruction references and remap StableIDs during explicit function cloning.
* [CodeGen] Add MIR function and block attributesRichard-Qin-X2026-08-011-0/+6
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* [CodeGen] Add target register descriptionsRichard-Qin-X2026-08-011-7/+13
| | | | Introduce an immutable register topology for units, subregisters, classes, banks, and preserved masks. Bind instruction descriptors to this topology through TargetDescription so builders, cloning, and verification share one target-aware contract. Add the test-only TestTarget model and positive and negative target fact coverage.
* [CodeGen] Add target state and compilation statusRichard-Qin-X2026-08-011-0/+22
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* [CodeGen] Add constant and jump table stateRichard-Qin-X2026-08-011-1/+40
| | | | Add stable, tombstone-preserving MachineConstantPool and MachineJumpTableInfo ownership. Define the versioned TargetConstant contract and integrate all table references with builders, verification, and deterministic deep cloning.
* [CodeGen] Add MachineFrameInfoRichard-Qin-X2026-08-011-1/+44
| | | | Model stable frame indices, stack object kinds, tombstones, lifetimes, and frozen layouts. Validate owned frame references in the builder and verifier, and remap complete frame state during MachineFunction cloning.
* [CodeGen] Add strict MachineIR verificationRichard-Qin-X2026-08-011-0/+504
Verify arena catalogs, intrusive layouts, reciprocal CFG edges, operand ownership, exact def-use coverage, instruction descriptors, pseudo deadlines, and MachineFunctionProperties. Preserve monotonic-arena history while rejecting detached objects that retain live state.