aboutsummaryrefslogtreecommitdiff
path: root/backend/lib/Tooling/PipelineDriver.cpp
Commit message (Collapse)AuthorAgeFilesLines
* [CodeGen] Add target machine registryRichard-Qin-X2026-08-281-94/+43
|
* [CodeGen] Implement reaching-def analysis printingRichard-Qin-X2026-08-261-2/+11
|
* [CodeGen] Implement RISC-V machine outliningRichard-Qin-X2026-08-251-3/+64
|
* [RISCV] Match LLVM emergency spill layoutRichard-Qin-X2026-08-241-2/+5
|
* [RISCV] Match LLVM frame lowering semanticsRichard-Qin-X2026-08-241-4/+12
|
* [CodeGen] Match LLVM machine debug strippingRichard-Qin-X2026-08-221-0/+8
|
* [CodeGen] Generate RISC-V macro fusion rulesRichard-Qin-X2026-08-221-2/+23
|
* [RISCV][GlobalISel] Select and expand global addressesRichard-Qin-X2026-08-191-1/+1
|
* [RISCV][GlobalISel] Legalize floating-point remainderRichard-Qin-X2026-08-151-2/+13
|
* [GlobalISel] Match LLVM CSE builder result semanticsRichard-Qin-X2026-08-151-4/+6
|
* [CodeGen] Match LLVM machine copy propagationRichard-Qin-X2026-08-131-2/+10
|
* [Tooling] Avoid unchecked pipeline selectorsRichard-Qin-X2026-08-131-3/+2
|
* [Tooling] Remove the duplicate output kindRichard-Qin-X2026-08-131-4/+24
|
* [CodeGen] Align MIR parser and printer ownershipRichard-Qin-X2026-08-131-1/+1
|
* [CodeGen] Align pass manager ownershipRichard-Qin-X2026-08-131-4/+4
|
* [RISCV] Split the GlobalISel target componentsRichard-Qin-X2026-08-121-14/+18
|
* [Tooling] Complete the LLVM MIR command-line contractRichard-Qin-X2026-08-121-26/+79
|
* [Tooling] Adopt LLVM MIR command-line spellingsRichard-Qin-X2026-08-121-3/+3
|
* [MIR] Remove alternate layout and float APIsRichard-Qin-X2026-08-121-1/+0
|
* [RISCV] Honor invocation subtarget featuresRichard-Qin-X2026-08-111-10/+17
|
* [MIR] Accept fixed-baseline LLVM syntaxRichard-Qin-X2026-08-111-0/+2
|
* [Tooling] Complete backend tooling and validationRichard-Qin-X2026-08-101-0/+436
generated by cgit v1.2.3 (git 2.46.0) at 2026-10-29 05:37:56 +0000