| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [MC] Implement RV64GC object emission | Richard-Qin-X | 2026-08-09 | 1 | -0/+30 |
| * | [MC] Implement RV64GC assembly emission | Richard-Qin-X | 2026-08-09 | 1 | -0/+13 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -0/+13 |
| * | [CodeGen] Implement RV64GC frame lowering | Richard-Qin-X | 2026-08-09 | 1 | -0/+13 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -0/+13 |
| * | [CodeGen] Implement machine SSA exit | Richard-Qin-X | 2026-08-08 | 1 | -0/+7 |
| * | [CodeGen] Implement RV64GC legalization and instruction selection | Richard-Qin-X | 2026-08-08 | 1 | -0/+7 |
| * | [CodeGen] Complete machine pass and ABI lowering infrastructure | Richard-Qin-X | 2026-08-07 | 1 | -0/+7 |
| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 1 | -1/+20 |
| * | [CodeGen] Add target register descriptions | Richard-Qin-X | 2026-08-01 | 1 | -0/+17 |
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