| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Support absolute address operand flags | Richard-Qin-X | 2026-08-12 | 1 | -3/+5 |
| * | [RISCV] Model typed floating-point register views | Richard-Qin-X | 2026-08-11 | 1 | -13/+27 |
| * | [RISCV] Add LP64 calling-convention facts | Richard-Qin-X | 2026-08-11 | 1 | -10/+20 |
| * | [RISCV] Derive the generated instruction count in tests | Richard-Qin-X | 2026-08-11 | 1 | -1/+5 |
| * | [CodeGen] Implement machine optimization and scheduling | Richard-Qin-X | 2026-08-09 | 1 | -2/+2 |
| * | [RISCV] Complete RV64GC instruction description | Richard-Qin-X | 2026-08-07 | 1 | -2/+95 |
| * | [RISCV] Add generated RV64GC register description | Richard-Qin-X | 2026-08-07 | 1 | -0/+109 |
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| A collection of projects, including a C compiler, binutils, a memory allocator, an automated theorem prover, and a web browser. |
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