| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | feat: Complete CSR/privileged/exception interrupt path and fill in strict ↵ | Richard Qin | 2026-04-01 | 1 | -0/+7 |
| | | | | | | | | | | | | | | | | | | acceptance tests - Refactor trap/CSR data path in the Core, unified with trap_ctrl interface to drive CSR update and return process - Improve critical paths for exception/interrupt handling: ecall, illegal, load fault, external interrupt, mret/sret return - Adjust pipeline stage registers with flush/stall coordination, fix residual control signal issues in trap scenarios - Enhance decode and related pipeline module behavior consistency, fill in missing control signal propagation across registers - Expand core integration testing, add trap/interrupt scenarios and CLI dispatch that can be executed per case - Extend CSR unit test coverage: read/write semantics, privilege switching, delegation and nested returns, illegal access protection, etc. - Register new core scenario cases in CTest to form a regression-capable P2 strict acceptance suite Verification: - Build passed - Full CTest passed (22/22) | ||||
| * | Trap Control unit and tests | Richard Qin | 2026-03-19 | 1 | -0/+10 |
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| * | CSR unit and tests | Richard Qin | 2026-03-19 | 1 | -9/+11 |
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| * | CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard Unit | Richard Qin | 2026-03-18 | 1 | -8/+24 |
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| * | Hazard unit and tests | Richard Qin | 2026-03-18 | 1 | -0/+9 |
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| * | Write Back stage unit and tests | Richard Qin | 2026-03-18 | 1 | -0/+9 |
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| * | Memory Stage and MEM/WB pipeline stage register | Richard Qin | 2026-03-18 | 1 | -0/+18 |
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| * | EX/MEM Pipeline Register unit and tests | Richard Qin | 2026-03-17 | 1 | -0/+9 |
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| * | Execute Stage unit and tests | Richard Qin | 2026-03-17 | 1 | -0/+11 |
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| * | ID/EX Pipeline Register and tests | Richard Qin | 2026-03-17 | 1 | -0/+9 |
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| * | IF/ID RegFile and tests | Richard Qin | 2026-03-17 | 1 | -0/+9 |
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| * | Instruction Decoder Stage unit and tests | Richard Qin | 2026-03-17 | 1 | -0/+11 |
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| * | Instruction fetching stage unit and test | Richard Qin | 2026-03-16 | 1 | -0/+9 |
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| * | branch unit and test | Richard Qin | 2026-03-16 | 1 | -0/+9 |
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| * | Decoder unit and test | Richard Qin | 2026-03-16 | 1 | -9/+9 |
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| * | Register file unit and test | Richard Qin | 2026-03-16 | 1 | -13/+13 |
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| * | Add and test alu unit | Richard Qin | 2026-03-15 | 1 | -8/+8 |
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| * | initial commit: project architecture | Richard Qin | 2026-03-15 | 1 | -0/+99 |
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