| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Hazard unit and tests | Richard Qin | 2026-03-18 | 1 | -0/+9 |
| * | Write Back stage unit and tests | Richard Qin | 2026-03-18 | 1 | -0/+9 |
| * | Memory Stage and MEM/WB pipeline stage register | Richard Qin | 2026-03-18 | 1 | -0/+18 |
| * | EX/MEM Pipeline Register unit and tests | Richard Qin | 2026-03-17 | 1 | -0/+9 |
| * | Execute Stage unit and tests | Richard Qin | 2026-03-17 | 1 | -0/+11 |
| * | ID/EX Pipeline Register and tests | Richard Qin | 2026-03-17 | 1 | -0/+9 |
| * | IF/ID RegFile and tests | Richard Qin | 2026-03-17 | 1 | -0/+9 |
| * | Instruction Decoder Stage unit and tests | Richard Qin | 2026-03-17 | 1 | -0/+11 |
| * | Instruction fetching stage unit and test | Richard Qin | 2026-03-16 | 1 | -0/+9 |
| * | branch unit and test | Richard Qin | 2026-03-16 | 1 | -0/+9 |
| * | Decoder unit and test | Richard Qin | 2026-03-16 | 1 | -9/+9 |
| * | Register file unit and test | Richard Qin | 2026-03-16 | 1 | -13/+13 |
| * | Add and test alu unit | Richard Qin | 2026-03-15 | 1 | -8/+8 |
| * | initial commit: project architecture | Richard Qin | 2026-03-15 | 1 | -0/+99 |
