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* M/S/U Mode csr pakageRichard Qin2026-03-181-0/+110
* Add fibonacci tests and fix bugsRichard Qin2026-03-183-8/+77
* fixed vm_trace bugRichard Qin2026-03-181-6/+6
* CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-185-8/+1252
* Hazard unit and testsRichard Qin2026-03-183-0/+446
* test(core): fix WB stage tests after naming and logic refactorRichard Qin2026-03-171-5/+8
* refactor(core): address WB stage architectural and naming review feedbackRichard Qin2026-03-171-12/+17
* Write Back stage unit and testsRichard Qin2026-03-183-0/+240
* docs: Finalized Richard CPU RTL architectural and naming convention audit rep...Richard Qin2026-03-1713-20/+1190
* Execute Stage unit and testsRichard Qin2026-03-173-0/+343
* ID/EX Pipeline Register and testsRichard Qin2026-03-173-0/+354
* IF/ID RegFile and testsRichard Qin2026-03-173-0/+193
* Instruction Decoder Stage unit and testsRichard Qin2026-03-173-0/+345
* Instruction fetching stage unit and testRichard Qin2026-03-163-0/+180
* branch unit and testRichard Qin2026-03-164-0/+174
* format outputRichard Qin2026-03-163-13/+20
* expand tests and format outputRichard Qin2026-03-163-9/+124
* fix naming problemsRichard Qin2026-03-167-84/+77
* Naming conventionRichard Qin2026-03-161-0/+159
* Decoder unit and testRichard Qin2026-03-163-9/+697
* Register file unit and testRichard Qin2026-03-163-13/+172
* LicenseRichard Qin2026-03-151-0/+17
* Add and test alu unitRichard Qin2026-03-156-8/+241
* initial commit: project architectureRichard Qin2026-03-1541-0/+2185
generated by cgit v1.2.3 (git 2.46.0) at 2026-11-09 14:56:31 +0000