| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [CodeGen] Implement the greedy register allocator pipeline | Richard-Qin-X | 2026-08-25 | 1 | -1/+1 |
| * | [RISCV] Match LLVM large call frame lowering | Richard-Qin-X | 2026-08-24 | 1 | -1/+1 |
| * | [RISCV] Match LLVM frame lowering semantics | Richard-Qin-X | 2026-08-24 | 1 | -21/+3 |
| * | [CodeGen] Match LLVM machine debug stripping | Richard-Qin-X | 2026-08-22 | 1 | -1/+2 |
| * | [MIR] Print target generic operand types | Richard-Qin-X | 2026-08-15 | 1 | -2/+2 |
| * | [CodeGen] Unify scalar low-level types | Richard-Qin-X | 2026-08-13 | 1 | -45/+5 |
| * | [MIR] Omit predictable successors in simplified output | Richard-Qin-X | 2026-08-13 | 1 | -6/+64 |
| * | [CodeGen] Preserve LLT annotations on generic opcodes | Richard-Qin-X | 2026-08-13 | 1 | -2/+3 |
| * | [IR] Split LL parsing, assembly writing, and data layout | Richard-Qin-X | 2026-08-13 | 1 | -10/+9 |
| * | [Support] Split APInt and APFloat ownership | Richard-Qin-X | 2026-08-13 | 1 | -2/+2 |
| * | [CodeGen] Align MIR parser and printer ownership | Richard-Qin-X | 2026-08-13 | 1 | -0/+3167 |
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