aboutsummaryrefslogtreecommitdiff
path: root/rv64cpu/tb/CMakeLists.txt
Commit message (Expand)AuthorAgeFilesLines
* checkpoint: preserve current RV64 CPU development stateRichard Qin4 days1-0/+29
* feat(tlb): add parameterized L1 TLB module and corresponding unit testsRichard Qin2026-04-011-0/+9
* feat(compliance): implement ACT4 strict compliance flow with ELF runnerRichard Qin2026-04-011-2/+2
* feat: Complete CSR/privileged/exception interrupt path and fill in strict acc...Richard Qin2026-04-011-0/+7
* Trap Control unit and testsRichard Qin2026-03-191-0/+10
* CSR unit and testsRichard Qin2026-03-191-9/+11
* CPU Core: Assembles a 5-stage pipeline, 4 inter-stage registers, and Hazard UnitRichard Qin2026-03-181-8/+24
* Hazard unit and testsRichard Qin2026-03-181-0/+9
* Write Back stage unit and testsRichard Qin2026-03-181-0/+9
* Memory Stage and MEM/WB pipeline stage registerRichard Qin2026-03-181-0/+18
* EX/MEM Pipeline Register unit and testsRichard Qin2026-03-171-0/+9
* Execute Stage unit and testsRichard Qin2026-03-171-0/+11
* ID/EX Pipeline Register and testsRichard Qin2026-03-171-0/+9
* IF/ID RegFile and testsRichard Qin2026-03-171-0/+9
* Instruction Decoder Stage unit and testsRichard Qin2026-03-171-0/+11
* Instruction fetching stage unit and testRichard Qin2026-03-161-0/+9
* branch unit and testRichard Qin2026-03-161-0/+9
* Decoder unit and testRichard Qin2026-03-161-9/+9
* Register file unit and testRichard Qin2026-03-161-13/+13
* Add and test alu unitRichard Qin2026-03-151-8/+8
* initial commit: project architectureRichard Qin2026-03-151-0/+99
generated by cgit v1.2.3 (git 2.46.0) at 2026-11-10 16:38:30 +0000