| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [CodeGen] Implement the greedy register allocator pipeline | Richard-Qin-X | 2026-08-25 | 1 | -0/+4 |
| * | [RISCV][GlobalISel] Generate indirect branch selection | Richard-Qin-X | 2026-08-19 | 1 | -1/+2 |
| * | [RISCV] Use the generated opcode conversion | Richard-Qin-X | 2026-08-13 | 1 | -10/+6 |
| * | [RISCV] Split the GlobalISel target components | Richard-Qin-X | 2026-08-12 | 1 | -1/+1 |
| * | [RISCV] Make target memory operands optional | Richard-Qin-X | 2026-08-12 | 1 | -1/+3 |
| * | [RISCV] Model typed floating-point register views | Richard-Qin-X | 2026-08-11 | 1 | -7/+14 |
| * | [RISCV] Match LLVM call-frame pseudo semantics | Richard-Qin-X | 2026-08-11 | 1 | -32/+0 |
| * | [CodeGen] Implement RV64GC frame lowering | Richard-Qin-X | 2026-08-09 | 1 | -0/+84 |
| * | [CodeGen] Complete register allocation infrastructure | Richard-Qin-X | 2026-08-09 | 1 | -0/+279 |
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